The present invention relates to methods and systems for analyzing and improving the net chip yield from a wafer by optimizing a laser anneal path in semiconductor manufacturing.
The chip yield for a wafer refers to the percentage of functional semiconductor chips on the wafer to the total number of semiconductor chips on the wafer. The chip yield can be estimated by measuring various test macros that are incorporated into each semiconductor chip by design, and can be tested at various test levels during manufacturing. The test macros provide reliable estimates of various processing parameters that are indicative of functionality of each semiconductor chip.
Some of the processing parameters measure anneal-activated parameters. An “anneal-activated” parameter refers to a measurable parameter that requires an anneal process in order to achieve a target value. For example, anneal-activated parameters include post-anneal sheet resistance of a metal silicide film, post-anneal sheet resistance of various doped semiconductor region, and leakage current measurement for gate dielectrics or node dielectrics. A measured value for an anneal-activated parameter within a target range at a test step is indicative of functionality of a semiconductor chip as far as the anneal-activated parameter is concerned.